1. Field of the Invention
The present invention generally relates to the manufacturing of metal-oxide-semiconductor field effect transistors (MOSFETs), and more particularly to MOSFETs manufactured for reproducibility of threshold voltages among otherwise identical transistors.
2. Prior Art
Random variation in threshold voltage (σVT) of metal-oxide semiconductor (MOS) field effect transistors (MOSFETs) with high-K (high dielectric constant) metal gate stack is caused by some dominant factors: (i) random dopant fluctuations (RDF) in the well and in the pocket implant regions underneath the gate, which, among other things, cause variations in depletion layer thickness; (ii) line edge roughness (LER) which causes random variation in the length of the gate electrode resulting from random variations in pattern of the etched gate; and, (iii) metal gate granularity (MGG) which causes random variations in the local work function due to the grain structure of the gate material. There is a fourth source of variation, the random variations in the effective channel length, referred to as random extension fluctuations (RXF), arising from statistical variations in the position of the junction that separates the channel from either the source or the drain extensions. However, as MOSFETs become smaller, the effects of RDF, LER, and RXF increase and become major factors in determining σVT. The first effect, RDF, has recently gained intense attention. The randomness in the position of the drain extension RXF has two principal sources: a) variations in the final position of implanted ions due to scattering; and, b) variations in the activation and positions of the source/drain extension ions as influenced by the activation and subsequent heat treatments.
It is well-known in the art that as MOSFETs move to smaller and smaller dimensions, variability of the threshold voltage σVT seriously undermines the reproducibility of threshold voltages among otherwise identical transistors. This effect is inevitable, and it is particularly severe in its impact on complimentary MOS (CMOS) static random access memories (SRAM), which use millions of near-minimum sized transistors. Development of ultra-thin silicon on insulator (SOI) structures, e.g., fully depleted SOI (FDSOI), and of three-dimensional transistors (FinFET and Tri-Gate), are largely motivated by a need to reduce the threshold voltage spreads σVT caused by RDF. This CMOS technology transition away from the more traditional bulk MOS manufacturing adversely impacts costs and availability.
One method of addressing the RDF problem was described by Asenov and Saini in the paper “Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-μm MOSFETs with Epitaxial and δ-Doped Channels,” IEEE Transactions on Electron Devices, Vol. 46, No. 8, August 1999, Pages 1718-1724. This approach is consistent with bulk transistors, and does not have the same cost penalties associated with FinFETs and FDSOI. This scheme has three key components: a) placing a thin, approximately 10 nanometer (nm), undoped epitaxial layer immediately beneath the gate oxide; b) placing a thinner layer with a very high concentration of either acceptors for an NMOS device or donors for a PMOS device at the boundary of the thin epitaxial layer that is remote from the gate dielectric interface; and, c) incorporating a moderately heavily doped well layer beneath the un-doped epitaxial layer and the highly doped, thinner layer. Asenov uses hundreds of simulations with Monte Carlo variations of the charge status at each atomic site within the transistor structure. FIG. 1 shows simulation curves from this prior art without a δ-layer, demonstrating that the σVT is a function of the thickness of an undoped epitaxial layer. A conventional transistor is equivalent to depi=0 in this figure. Implicit in this curve is the fact that, for a given charge density beneath the epitaxial layer, the electrostatic component of the threshold voltage diminishes with increasing thickness of that layer. FIG. 1 also shows that there may be a range of optimum values for the epi thickness. This work was expanded by Roy, Brown and Asenov in “Random dopant fluctuation resistant ‘bulk’ MOSFETs with epitaxial delta doped channels,” presented at the 2007 ULSI Conference. In this work, it is shown that the thickness of an undoped epitaxial layer reduces the threshold voltage variations as shown in FIG. 2, but it also tends to lower the threshold voltage as shown in FIG. 3. This means that the definition of the epi layer and the doping beneath it represent a design trade-off.
Similar structures have been subsequently demonstrated by Fujita et al. as described in their paper “Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications”, Electron Devices Meeting (IEDM), 2011 IEEE International, pp. 32.3.1-32.3.4, 5-7 Dec. 2011. A related approach to realizing an epitaxial transistor has been patented by Thompson and Thummalapally in “Electronic devices and systems, and methods for making and using the same,” U.S. Pat. No. 8,273,617, Sep. 25, 2012.
Recent changes to gate architectures from poly-silicon over silicon dioxide or oxynitride, to metal over high-K gate dielectric stack have changed the processing sequence. (A high-K or high dielectric constant as used herein and in the claims to follow means a dielectric constant that is higher than the dielectric constant of silicon dioxide for which K=3.9; an effective dielectric constant K exceeding 6 would be a preferred high-K.) This is particularly true for the “gate last” process flow. In this process, while there is seemingly a complete transistor, with oxide and/or nitride sidewall spacers on each side of a poly gate, the gate is actually a sacrificial structure. That gate structure and the underlying protective oxide are etched away, exposing the silicon surface. Then a sequence of steps is employed: a) deposition of a high-K gate dielectric, typically by atomic layer deposition; b) deposition of a metal gate having a controlled work function to set the threshold voltage; and, c) deposition of a robust gate material, typically doped amorphous silicon. In many cases the sequence above is augmented by chemical-mechanical polishing steps to assure the localization of the various layers. However, this structure does not overcome the deficiencies resulting from RDF, LER or RXF. The morphology of the metal in the gate last process does reduce the variations identified as MGG, compared to a gate first process.
Structures which address all variations, RDF, LER and RXF, have been described by Asenov in “Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET)” U.S. App 2013/0049140 (Feb. 28, 2013). Similar structures lacking consideration for random doping density fluctuations have been described by Sugihara, et al. (“Semiconductor device,” U.S. Pat. No. 6,566,734, May 20, 2003) and by Lee, et al. (“Method for fabricating a semiconductor device using a damascene process,” U.S. Pat. No. 6,627,488, Sep. 30, 2003). All three authors require the growth of a thin layer of epitaxial semiconductor in a nominally square, etched recess. This type of epitaxial growth could be heavily subject to faceting and the creation of defects along the sidewalls. The resulting defects create leakage to the substrate, potential barriers in the current path and weak spots in the gate oxide.
FIG. 4 shows an exemplary cross-section of the essential parts of a transistor formed without the benefits of this invention. A silicon substrate 100 is partitioned to support individual transistors by shallow trench isolation 102. The transistor per se is defined by a source and drain 104. Because of the symmetry of the illustrative FET, the source and drain are both given the same identifying number. In order to reduce parasitic resistance, the sources and drains are buttressed with low resistance epitaxial layers 106. The channel region 108 consists of zero or very lightly doped epitaxial silicon. Beneath that, region 110 is very highly doped, P-type for NMOS transistors or N-type for PMOS transistors. The gate structure consists of a high-K gate dielectric 112, a metallic gate 114 and a protective gate “handle” 116. The gate structure is separated from interlayer dielectric 118 by dielectric gate spacers 120. Of particular note is the shape of the epitaxial region 108; it is square, possibly with [110] sidewalls. This configuration is at risk for creating facets during the growth of the zero-doped epitaxial layer. Facets would interrupt the channel surface, creating sites with excessive leakage in the gate dielectric and scattering discontinuities in the conductive channel and degrading both device performance and repeatability among otherwise “identical” devices.
It would therefore be advantageous to find a solution that has the advantages of reducing all the sources of variation, as described by Asenov, but offered a favorable configuration for growing the necessary epitaxy without facets.